The present invention relates to a manufacturing process for a power semiconductor device, which utilizes a flexible metal tape carrier for automation purposes, and also to power semiconductor devices produced from such manufacturing process.
Manufacturing of semiconductor devices typically includes the attachment of electrical leads to the electrodes of a semiconductor chip. To avoid the expense of labor-intensive joining of electrical leads to electrodes of a chip, a Tape Automated Bond (TAB) process has been developed for "signal" chips, such as used in digital watches or calculators. In the TAB process, a flexible tape carrier is used in the formation of electrical leads for individual signal chips. In particular, the flexible tape comprises a non-conducting, plastic main layer with a thin copper layer, typically of 1.3 mils (0.0013-inch) thickness, atop the plastic layer. Electrical leads for the signal chips are provided through appropriate configuration of the thin copper layer atop the plastic layer.
The unique requirements of power semiconductor chips, which typically dissipate heat in excess of about 10 watts per cm.sup.2, preclude the use of tape carriers used in the TAB process for manufacturing signal level semiconductor devices. This is because (1) the copper on the TAB flexible tape carriers is not sufficiently thick to accommodate the large currents of power semiconductor chips, and (2) the large size of typical power semiconductor chips, which may reach dimensions as large as 0.750 inches, results in a severe thermal expansion mismatch between the tape carrier and the power chip, thereby placing the power chip in danger of warping or fracturing.
If the copper layer on the TAB tape carriers is increased in thickness so as to handle the large currents of power semiconductor chips, the thermal mismatch between tape carrier and chip is aggravated.
It would thus be desirable to provide a tape automated manufacturing process accommodating the requirements of power semiconductor devices.
The manufacturing of power semiconductor devices can also greatly benefit from permitting full electrical testing of power chips prior to their being incorporated in a relatively expensive device package. This is especially true where power chips are paralleled in a circuit to provide high current capacity, since one defective power chip in a paralleled arrangement would render the entire assembly useless.